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 HD74HC259
8-bit Addressable Latch
REJ03D0603-0200 (Previous ADE-205-480) Rev.2.00 Jan 31, 2006
Description
The HD74HC259 has a single data input (D), 8 latch outputs (Q0-Q7), 3 address inputs (A, B, and C), a common enable input (E), and a common clear input. To operate this device as an addressable latch, data is held on the D input, and the address of the latch into which the data is to be entered is held on the A, B and C inputs. When enable is taken low the data flows through to the addressed output. The data is stored when enable transitions from low to high. All unaddressed latches will remain unaffected. With enable in the high state the device is deselected, and all latches remain in their previous state, unaffected by changes on the data or address inputs. To eliminate the possibility of entering erroneous data into the latches, the enable should be held high (inactive) while the address lines are changing. If enable is held high and clear is taken low all eight latches are cleared to a low state. If enable is low all latches except the addressed latch will be cleared. The addressed latch will instead follow the D input, effectively implementing a 3to-8 line decoder.
Features
* * * * * * High Speed Operation: tpd (Data to Output) = 16 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 A max Low Quiescent Supply Current: ICC (static) = 4 A max (Ta = 25C) Ordering Information
Part Name HD74HC259P HD74HC259FPEL HD74HC259RPEL Package Type DILP-16 pin SOP-16 pin (JEITA) SOP-16 pin (JEDEC) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) PRSP0016DG-A (FP-16DNV) Package Abbreviation P FP RP -- EL (2,000 pcs/reel) EL (2,500 pcs/reel) Taping Abbreviation (Quantity)
Note: Please consult the sales office for the above package availability.
Rev.2.00 Jan 31, 2006 page 1 of 9
HD74HC259
Function Table
Inputs Clear H H L L G L H L H Output of Addressed Latch D Qio D L Select Inputs C L L L L H H H H B L L H H L L H H A L H L H L H L H Each Other Output Qio Qio L L Function Addressable latch Memory 8-line demultiplexer Clear
Latch Addressed 0 1 2 3 4 5 6 7
Notes: 1. D: the level at the data input 2. Qio: the level of Qi (i = 0, 1, ***7, as appropriate) before the indicated steady-state input conditions were established.
Pin Arrangement
A Latch select B C Q0 Q1 Outputs Q2 Q3 GND 6 7 8 Q2 Q3 Q4 Q6 Q5 11 Q6 Outputs 10 Q5 9 Q4 1 2 3 4 5 B C Q0 Q1 A CLR G D Q7 16 VCC 15 Clear 14 Enable 13 Data input
12 Q7
(Top view)
Rev.2.00 Jan 31, 2006 page 2 of 9
HD74HC259
Absolute Maximum Ratings
Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC VIN, VOUT IIK, IOK IO ICC or IGND PT Tstg Ratings -0.5 to 7.0 -0.5 to VCC +0.5 20 25 50 500 -65 to +150 Unit V V mA mA mA mW C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time*1 Symbol VCC VIN, VOUT Ta tr, tf Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500 0 to 400 Unit V V C ns Conditions
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Item Input voltage Symbol VCC (V) VIH 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- Ta = 25C Typ Max -- -- -- -- -- -- 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.1 4.0 Ta = -40 to+85C Unit Min Max 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 1.0 40 V Test Conditions
VIL
V
Output voltage
VOH
V
Vin = VIH or VIL IOH = -20 A
IOH = -4 mA IOH = -5.2 mA V Vin = VIH or VIL IOL = 20 A
VOL
Input current Quiescent supply current
Iin ICC
IOL = 4 mA IOL = 5.2 mA A Vin = VCC or GND A Vin = VCC or GND, Iout = 0 A
Rev.2.00 Jan 31, 2006 page 3 of 9
HD74HC259
Switching Characteristics
(CL = 50 pF, Input tr = tf = 6 ns)
Item Propagation delay time Symbol VCC (V) tPHL tPLH 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Hold time th 2.0 4.5 6.0 2.0 4.5 6.0 -- Ta = 25C Min Typ Max -- -- 185 -- 16 37 -- -- 31 -- -- 215 -- 20 43 -- -- 37 -- -- 200 -- 17 40 -- -- 34 -- -- 155 -- 15 31 -- -- 26 80 -- -- 16 6 -- 14 -- -- 100 -- -- 20 17 5 5 5 -- -- -- -- 5 -- -- -1 -- -- 5 -- 5 -- -- -- -- -- 75 15 13 10 Ta = -40 to +85C Unit Test Conditions Min Max -- 230 ns Data to output -- 46 -- 39 -- 270 ns Latch select to output -- 54 -- 46 -- 250 ns Enable to output -- 50 -- 43 -- 195 ns Clear to output -- 39 -- 33 100 -- ns Clear, Enable 20 -- 17 -- 125 -- ns Latch select or data to enable 25 21 5 5 5 -- -- -- -- -- -- -- -- -- 95 19 16 10 ns Latch select or data to enable
tPHL
Pulse width
tw
Setup time
tsu
Output rise/fall time Input capacitance
tTLH tTHL Cin
ns
pF
Test Circuit
VCC VCC
G
See Function Table
Input Pulse Generator Zout = 50
Output Q0 to Q7 CL = 50 pF
Clear A B C D
Note : 1. CL includes probe and jig capacitance.
Rev.2.00 Jan 31, 2006 page 4 of 9
HD74HC259
Waveforms
* Waveform - 1
tf
90%
tr
90% 10%
VCC 0V tr
90% 50% 10% 10%
Enable G
10%
tf Clear
90% 50%
VCC 0V
tw (Clear) tPHL Addressed Output Q
90% 50% 10%
VOH VOL
tTHL Notes : 1. Input pulse : PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. D = VCC , Unaddressed Q = L
* Waveform - 2
tr Data
10% 90% 50% 90% 50% 10%
tf VCC 0V
tPLH
90%
tPHL
90% 50% 10%
VOH VOL
Output Q
50% 10%
tTLH
tTHL
Notes : 1. Input pulse : PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. Other input : G = GND, Clear = Vcc, A to C = Address
Rev.2.00 Jan 31, 2006 page 5 of 9
HD74HC259
* Waveform - 3
VCC Data 0V tf
90 % 50 % 10 % 10 %
tr
90 % 50 %
VCC
50 %
Address (A to C)
0V t PHL
t PLH Addressed Output Q
90 % 50 % 10 %
90 % 50 % 10 %
VOH VOL
t TLH Addressed Output Q
t THL VOH VOL
Notes : 1. Input pulse : PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. Other input : G = GND, Clear = VCC, A to C = Address
* Waveform - 4
VCC Data
50% 50% 50%
tsu(H) tf G
90% 50% 10% 10%
th(H) tr
90% 50%
tsu(L)
th(L)
0V
VCC
50% 50%
tw(G) tPLH
90%
0V tPHL
90% 50% 10%
VOH VOL
Qn
50% 10%
tTLH
tTHL
Notes : 1. Input pulse : PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. Other input : Clear = VCC, A to C = Address
Rev.2.00 Jan 31, 2006 page 6 of 9
HD74HC259
* Waveform - 5
VCC Data 0V VCC
50 % 50 % 50 % 50 %
Address Input
0V tsu th tsu th VCC G
50 % 50 %
0V
VOH Qn VOL
Notes : 1. Input pulse : PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. Other input : Clear = VCC 3. Address inputs except appropriate inputs are set to address to appropriate Q outputs.
Rev.2.00 Jan 31, 2006 page 7 of 9
HD74HC259
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
E
A1
A
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max
e D E
L
1
A A1
e
bp
e1
b c b c
p 3
e Z ( Ni/Pd/Au plating ) L
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c
0.00
0.10
0.20 2.20
0.34
0.40
0.46
0.15
1
0.20
0.25
A
c
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.2.00 Jan 31, 2006 page 8 of 9
HD74HC259
JEITA Package Code P-SOP16-3.95x9.9-1.27 RENESAS Code PRSP0016DG-A Previous Code FP-16DNV MASS[Typ.] 0.15g
*1
D 9
F
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
Index mark
*2
E
HE
c
Reference Symbol
Dimension in Millimeters Min Nom 9.90 3.95 Max 10.30
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c c
1
0.10
0.14
0.25 1.75
0.34
0.40
0.46
0.15
0.20
0.25
HE
0 5.80 6.10 1.27
8 6.20
A
A1
L y
e x y
0.25 0.15 0.635 0.40
1
Detail F
Z L L 0.60 1.08
1.27
Rev.2.00 Jan 31, 2006 page 9 of 9
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 205, AZIA Center, No.133 Yincheng Rd (n), Pudong District, Shanghai 200120, China Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
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Colophon .5.0


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